A certain type of flash memory array uses a p-channel MOS transistor as the storage element and a p-channel MOS transistor as the control element in each memory cell. This type of flash memory can have a large number of memory cells, for example, 2 million or 4 million such cells arranged typically in a 1K by 2K or 1K by 4K configuration. Each memory cell will contain a control transistor and a floating gate transistor. The floating gate of the floating gate transistor will be programmed to either contain a charge (which typically will turn on the floating gate transistor) or no charge (which typically will leave off the floating gate transistor). Thus binary information (i.e. a one (“1”) or a zero (“0”) can be stored in the floating gate transistor.
Small portions of two typical prior art flash memory arrays are illustrated in FIGS. 1c and 1d. FIGS. 1c and 1d each show an array of memory cells with control transistors Q11 through QRC (where R equals the number of rows in the array, C equals the number of columns in the array and RC equals the number of memory cells in the array) and floating gate transistors F11 through FRC. Each control transistor Qrc (where 1≦r≦R and 1≦c≦C) is associated with a corresponding floating gate transistor Frc in a memory cell rc. Floating gate transistors F11 through FRC are shown in the arrays of FIGS. 1c and 1d. Each floating gate transistor Frc contains a floating gate (139 in FIG. 1c and 149 in FIG. 1d) which will store or not store charge depending upon the information to be stored in each memory cell.
FIG. 1a shows in cross section the structure of a typical P-type transistor Q11. In FIG. 1a, P-type regions 102a and 102b are formed, typically by ion implantation, in an N-type substrate or N well 101. P-type regions 102a and 102b are separated from each other by a channel region 103 the conductivity type of which can be changed by a voltage applied to control gate 106 through conductive lead 107 in ohmic contact with gate 106. Gate insulation 105 is formed between control gate 106 and the underlying channel region 103.
The source of a P-type transistor is that one of the P-type regions 102a and 102b which is at a higher voltage than the other P-type region 102 when the P-type transistor is being used. Thus, during one operation, a given p-type region 102 might be the source of the p-type transistor. During another operation this same p-type region might be the drain of the p-type transistor. Typically, during programming, the control transistor Qrc and the floating gate transistor Frc will each have one p-type region be the source and the other p-type region be the drain whereas during readout of information stored on the floating gate transistor, the source and drain of each of these transistors can, in some embodiments, be reversed.
FIG. 1b shows a cross section of a typical MOS P-channel floating gate transistor 100b. The regions within floating gate transistor 100b which are identical in structure to the regions within control transistor 100a are identically numbered. Floating gate transistor 100b includes a floating gate 116 which is insulated from the underlying channel region 103 by gate insulation 105 and to which no other conductor is attached. During the charging of floating gate 116, current will flow from the source region of the floating gate transistor into the channel region 103 and electrons will be diverted through the gate insulation 105 onto the floating gate 116 as a result of a phenomenon known as hot electron injection or Fowler-Nordheim tunneling or both. As a result, electrons are placed on floating gate 116. Should the charge created by these electrons be sufficiently high, these electrons will cause inversion of the underlying channel region 103 from N-type to P-type thus providing a conductive path between the P-type regions 102a and 102b. When this conductive path exists in a given floating gate transistor Frc in a memory cell rc (see FIGS. 1c and 1d), and the control transistor Qrc in that memory cell rc is turned on, a current will flow through memory cell rc if a voltage drop is created across memory cell rc. The current will indicate the nature of the information stored in the memory cell rc. If no charge has been placed on the floating gate 116 of floating gate transistor Frc (100b in FIG. 1b), then no current will flow through memory cell rc when a voltage is placed across memory cell rc and control transistor Qrc is turned on. Thus a binary one (“1”) or zero (“0”) is stored in each memory cell rc and the state of the memory cell is detected by the presence or absence of current when a voltage is placed across the memory cell and the control transistor Qrc is turned on.
Typically, to program a floating gate transistor such as F11 (FIG. 1c), a minus eight (−8) volts programming voltage is applied to the gate 133-11 of control transistor Q11 from X-decoder 132 by means of lead 137-1. Simultaneously, minus five (−5) volts is applied from Y-line decoder 131 by means of lead 136-1 to P-type region “b” of P-type transistor Q11. Row interconnect 137-1 connects and thus applies the same voltage to the gates of all control transistors in row 137-1 which is minus eight (−8) volts during programming of one or more memory cells connected to the row. However, if only F11 is being programmed, only the column line 136-1 will be placed at minus five (−5) volts. Thus, P-type transistor Q11 turns on and conducts current and causes P-type region “b” of floating gate transistor F11 to be slightly above approximately minus five (−5) volts due to the voltage drop across channel 103 of Q11. Because interconnect 138-1 is at ground potential, during programming P-type region “a” of floating gate transistor F11 acts as a source as does P-type region “a” of control transistor Q11. The P-type regions denoted “b” of control transistor Q11 and of floating gate transistor F11 will act as drains. With the voltages as described, current will flow from grounded lead 138-1 to lead 136-1 at minus five (−5) volts. This current will cause electrons to flow onto floating gate 139-11 of F11 thus creating a negative charge on this gate. This negative charge will cause the channel region 103 of floating gate transistor F11 to invert. Inverted channel 103 will allow current to flow between P region “a” and P region “b” of F11 should control transistor Q11 subsequently be turned on during subsequent readout of memory cell 11.
The minus eight (−8) volts required to turn on control transistor Q11 during the programming of floating gate transistor F11 is larger in absolute magnitude than the control transistor can sustain if the control transistor is manufactured using feature sizes under 0.18 microns. Accordingly, it is necessary to provide a structure which will allow the programming of floating gate transistors (such as F11) in the array of FIG. 1c using a gate voltage on the control transistors (such as gate 133-11 on Q11) smaller in absolute magnitude than eight (8) volts.
Note that when minus eight (−8) volts is applied to interconnect 137-1 and all the other control gates 133-12 (not shown) through 133-1C connected to interconnect 137-1 are at minus eight (−8) volts, the control transistors Q12 (not shown) through Q1C turn on but do not conduct current because the voltages on their column lines 136-2 (not shown) through 136-C are kept at zero (0) volts, the same as the voltage on grounded lead 138-1.
To read out the signal stored on floating gate transistor F11 during normal operation of the memory array, a voltage of minus three (−3) volts is applied to the control gate 133-11 of control transistor Q11 while a voltage of minus one point five (−1.5) volts is applied to column interconnect 136-1. Transistor Q11 turns on and current then flows from grounded interconnect 138-1 through floating gate transistor F11 because floating gate transistor F11 has had its channel region 103 inverted as a result of the electrons stored on floating gate 139-11. This current then passes through turned-on control transistor Q11 and is detected by the sense amp 130-1 (not shown) in sense amp block 130 connected to column line 136-1. The other transistors in row 137-1 which have their gates also held at minus three (−3) volts will not have a current flowing through them because their corresponding column lines 136-2 (not shown) through 136-C are held at zero (0) volts, the same as the voltage on grounded interconnect 138-1.
In one embodiment, all the memory cells connected to a given row can be read out simultaneously by having the bit lines 136-1 to 136-C brought to minus one point five (−1.5) volts. Each bit line 136-i is connected to a sense amp 130-i in sense amp block 130 thus allowing the states of the memory cells 11 to 1C to be read out simultaneously.
The alternative prior art structure shown in FIG. 1d allows programming of each floating gate transistor in the memory array with a lower voltage but results in an unpredictable increase in the capacitance sensed on the column line (i.e. the bit line) when reading out a floating gate transistor. This slows down the read out of data from each memory cell. As shown in FIG. 1d, this particular structure has floating gate transistor F11 with a P-type region “b” connected to column line 146-1 and P-type region “a” connected in series with P-type region “b” of control transistor Q11. P-type region “a” of control transistor Q11 is connected to grounded interconnect 148-1.
To program the floating gate transistor F11 in memory cell 11 of the memory cell array in FIG. 1d, the floating gate transistor F11 has its drain “b” held to about minus five (−5) volts by the voltage on column 146-1 being brought to minus five (−5) volts through Y-line decoder 141. Source “a” of floating gate transistor F11 is connected to drain “b” of control transistor Q11 and source “a” of control transistor Q11 is connected to grounded (i.e. at zero volts) interconnect 148-1 . A minus two (−2) volt potential is then applied to the gate 143-11 of select transistor Q11 from X-decoder 142 by means of row line 147-1. This same minus two (−2) volts is also applied to the gates 143 of all other control transistors Q1c connected to row line 147-1. Consequently, current flows from the source “a” of Q11 through Q11 to source “a” of floating gate transistor F11. This current passes through turned-on floating gate transistor F11 and some of the electrons from this current then charge the floating gate 149-11 of floating gate transistor F11 thereby resulting in a negative charge being stored on floating gate 149-11. Consequently, the channel region 103 underlying floating gate 149-11 is inverted resulting in current being capable of passing through floating gate transistor F11 whenever control transistor Q11 is turned on and a voltage is applied across the memory cell.
The prior art structure shown in FIG. 1d requires less of a voltage range to turn on and charge the floating gate of transistor F11 than the structure shown in FIG. 1c. However, in the embodiment of FIG. 1d, each floating gate transistor Frc which is turned on and attached to column 146-c (only columns 146-1 and 146-C are shown in FIG. 1d), allows the capacitance of that floating gate transistor to affect the turn-on speed of the sense amp 140-c in sense amp block 140 attached to that column. The sense amp 140-c attached to column 146-c senses the current through the floating gate transistor in the memory cell attached to that column being read. However, the speed of this sense amp 140-c is affected by the capacitances of all other floating gate transistors Frc with an inverted channel attached to that column.
For example, to read the state of a given memory cell in the memory array of FIG. 1d such as memory cell 11 made up of floating gate transistor F11 and select transistor Q11, minus three (−3.0) volts is applied from row line 147-1 to the gate 143-11 of transistor Q11 to turn on Q11. Minus one point five (−1.5) volts is applied from Y line decoder 141 to column line 146-1. Since lead 148-1 is grounded, a current will flow through transistor Q11 and floating gate transistor F11 (which has been turned on by the charge stored on floating gate 149-11). The sense amp 140-1 in sense amp structure 140 connected to column lead 146-1 will detect this current. If floating gate 143-11 contains no charge, then no current will flow through floating gate transistor F11 and no current will flow out to bit line 146-1 and no current will be detected by sense amp 140-1. The other cells attached to row line 147-1 with minus three (−3) volts applied thereto will remain off because their column lines 146-2 through 146-C will, in one embodiment, be maintained at zero volts during the reading of memory cell 11 attached to column line 146-1. However, if desired, all memory cells connected to row line 147-1 can be read out simultaneously.
In the memory array of FIG. 1c, the sense amp reading out the signal is impacted by only one channel capacitance, namely the channel capacitance associated with the control transistor of the floating gate transistor being read. For example, if there are 1,000 rows in the memory array, the sense amp senses only the channel capacitance associated with the control transistor connected to the bit line and turned on by the negative voltage on its row line and not the other 999 capacitances associated with the other 999 control transistors.
In the second prior art embodiment described above in FIG. 1d, the bit line capacitance is not fixed. The capacitance of a bit line can vary depending upon how many floating gate transistors Frc which are attached to the bit line have been programmed to be on because each turned-on floating gate transistor introduces additional capacitance to the bit line. The embodiment described in FIG. 1c above is more stable but the embodiment of FIG. 1d uses lower programming voltages so there is a trade-off between which embodiment to use.
Accordingly, it would be desirable to have the advantages of both of the prior art embodiments in one given structure. In particular, it would be desirable to have a structure which would provide both the low voltage capability of the prior art embodiment described in FIG. 1d together with the low capacitance of the embodiment described in FIG. 1c when a memory cell is being read.